SSD Qualification Engineer - PCIe Validation

Pure Storage

Santa Clara, California

Full Time

Posted May 8, 2026

$180k - $270k

Energy Storage

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Job Description

The role involves designing, executing, and debugging PCIe validation tests for SSDs, developing automated test frameworks, and collaborating with cross-functional teams to ensure protocol compliance and troubleshoot issues in a fast-paced, hands-on environment.

Key Responsibilities

Design and execute PCIe validation and debugging for SSDs, including link and protocol testing.
Develop and maintain automated PCIe test suites and frameworks using analyzers and exercisers.
Create PCIe test plans covering link training, resets, error injection, power management, and recovery behaviors.
Validate SSD behavior under abnormal and corner conditions and provide validation reports for milestones.
Triaging and analyzing failures by correlating PCIe traces, logs, and system data to identify root causes.
Collaborate with hardware, firmware, and systems teams to verify fixes and improve test coverage.
Leverage PCIe tools such as analyzers, exercisers, oscilloscopes, and logic analyzers for debugging.
Lead efforts to improve PCIe test coverage, standardize testing procedures, and share best practices.

Requirements

Six years of experience in SSD, storage, or PCIe centric validation bring up or equivalent embedded high speed I/O domain.
Strong understanding of PCIe fundamentals.
Hands-on experience using PCIe analyzers and exercisers (e.g., Teledyne LeCroy, Keysight, or similar) for trace capture and debug.
Proficiency with Python or similar programming languages for test and tooling development.
Ability to work effectively in Linux-based validation environments.
Experience with CI regression infrastructure such as Jenkins and Git-based workflows for large-scale test execution.
Strong debug skills across hardware, firmware, and system boundaries, with the ability to go from symptom to hypothesis to validated root cause.
Ability to define PCIe test plans covering link training, lane width and speed changes, resets, hot plug, surprise removal, error injection, power management states, and recovery behavior.
Experience executing PCIe validation tests including Gen4, Gen5, and Gen6 link and protocol tests across different platforms and system configurations.
Ability to validate SSD behavior under abnormal and corner conditions and provide periodic PCIe validation readouts for critical program milestones.
Experience developing and maintaining automated PCIe test content frameworks, integrating PCIe analyzers, exercisers, and tools into test frameworks to enable reproducible, automated scenarios.
Ability to triage failures from regression, bring-up, and customer scenarios by correlating PCIe traces, NVMe OCP logs, and system logs.
Experience partnering with firmware, hardware, and systems teams to root cause issues, verify fixes, and incorporate improvements into test suites.
Proficiency in leveraging PCIe tools such as analyzers and exercisers for trace capture and error injection, and using oscilloscopes, logic analyzers, BERTs, and related tools for signal and protocol level debugging.
Leadership in test roadmap development, including coverage improvements, standardizing PCIe test APIs, logs, and reporting for reuse across products, and sharing PCIe debug and test best practices.
Willingness to work from the Santa Clara, CA office in compliance with company policies, unless on PTO, work travel, or other approved leave.