Senior Signal and Power Integrity Engineer
Pure StorageSanta Clara, California
Full Time
Posted November 13, 2025
$175k - $263k
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Application opens on company website
Job Description
This role involves leading the Signal and Power Integrity strategy for high-performance storage platforms, overseeing electrical architecture, collaborating across teams to ensure system robustness, and driving design standards and validation processes for cutting-edge high-speed interfaces.
Key Responsibilities
- Lead the Signal and Power Integrity (SI/PI) strategy for high-performance storage platforms.
- Own the electrical architecture from concept to validation and compliance sign-off.
- Architect and manage SI strategies for high-speed interfaces such as PCIe Gen5, 800G Ethernet, DDR5.
- Establish and validate Power Delivery Network (PDN) targets, including impedance profiling and decoupling optimization.
- Define and enforce global design standards in collaboration with PCB and mechanical teams.
- Lead complex system-level debug, root-cause analysis, and corrective actions for SI/PI issues.
- Develop and standardize automated simulation workflows, reporting pipelines, and CI checks for hardware quality.
Requirements
- Expert-level proficiency in high-speed channel design and validation for modern interfaces such as PCIe Gen4, PCIe Gen5, 25G SerDes Ethernet, DDR4, and DDR5, including deep knowledge of electromagnetic theory, crosstalk mitigation, and jitter analysis.
- Mastery of industry-standard EDA tools such as Sigrity, ADS, HFSS, and HyperLynx for pre- and post-layout Signal Integrity (SI) and Power Integrity (PI) analysis, including IBIS-AMI, channel modeling, and hands-on lab validation using high-speed instruments like VNA, TDR, BERT, and oscilloscopes.
- Advanced Power Integrity design experience in target impedance methodology, VRM modeling, noise coupling analysis, and defining component placement strategies to mitigate simultaneous switching noise (SSN) and ground bounce.
- Demonstrated ability to lead technical initiatives and drive complex cross-functional decisions, acting as a facilitator and mentor to junior engineers while documenting best practices to champion quality by design.
- Fluency in developing scripts using Python or MATLAB for automating SI and PI model extraction, simulation workflows, post-processing, and generating standardized reports.
- Experience in defining and enforcing global design standards by collaborating with PCB layout and mechanical teams on stackups, materials, routing rules, and constraints to achieve first-pass silicon success and manufacturing quality.
- Ability to serve as the SI and PI technical lead for complex system-level debug, root-cause analysis, and corrective action implementation to resolve critical issues across prototypes, validation, and field escalations.
- Experience in establishing and validating Power Delivery Network (PDN) targets, including impedance profiling and decoupling optimization.
- Proficiency in owning the end-to-end electrical architecture, from high-level concept definition and advanced modeling to final lab validation and compliance sign-off.
- Ability to collaborate with Hardware Design, PCB Layout, and firmware teams to ship robust, high-performance storage products globally.
- Bachelor’s degree or higher in Electrical Engineering, Electronics, or related field.
- Physical ability to work in an office environment in Santa Clara, CA, in accordance with company policies, unless on PTO, work travel, or other approved leave.
Benefits & Perks
Salary range: 175,000 - 263,000 USD
Work in-office environment in Santa Clara, CA
Potential eligibility for incentive pay and equity
Flexible time off
Wellness resources
Company-sponsored team events
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