A Senior Firmware Engineer specializing in PCIe technologies, responsible for designing, developing, and debugging high-performance firmware for DirectFlash SSD modules, collaborating with hardware and software teams to create resilient storage solutions.
Key Responsibilities
Design and develop high-performance firmware for DirectFlash SSD Modules focusing on PCIe functionality
Lead the bring-up and integration of new PCIe-based hardware ensuring compliance and optimal link performance
Develop and maintain PCIe features such as LTSSM, power management, hot-plug support, and error handling
Debug complex system-level issues across firmware, drivers, and hardware
Collaborate with hardware engineering teams on PCIe PHY integration, validation, and signal integrity
Requirements
Deep expertise in firmware development for embedded systems, with a strong understanding of PCIe architecture, protocols, and hardware software interactions.
Proficiency in C and C++ programming languages.
Demonstrated ability to use scripting languages like Python for test automation and tooling.
Hands-on experience with PCIe firmware development, including LTSSM bring-up and debugging, link training, error recovery, and register-level programming.
Proven track record of debugging and resolving complex issues across firmware, hardware, and driver boundaries.
Experience with hardware bring-up on new platforms.
Experience using PCIe compliance tools such as protocol analyzers.
Ability to design and deliver high-performance firmware for DirectFlash SSD Modules, focusing on PCIe functionality including initialization, configuration, and runtime management.
Experience leading the bring-up and integration of new PCIe-based hardware, ensuring compliance with specifications and optimal link performance.
Experience developing and maintaining key PCIe features such as LTSSM, power management, hot-plug support, and robust error handling.
Ability to debug complex, system-level issues at the intersection of firmware, drivers, and hardware, and to build advanced diagnostics tools.
Ability to collaborate closely with hardware engineering teams on PCIe PHY integration, validation, and signal integrity considerations.
Willingness to work onsite at the Santa Clara, CA office in accordance with company policies.
Benefits & Perks
Salary range: 175,000 - 263,000 USD
Work environment: primarily in-office at Santa Clara, CA
Work schedule: flexible time off
Perks: wellness resources, company-sponsored team events
Additional benefits: incentive pay and/or equity, accommodations for disabilities, inclusive and diverse workplace culture
Ready to Apply?
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