Senior Signal and Power Integrity Engineer
Pure StorageSanta Clara, California
Full Time
Posted December 12, 2025
$175k - $263k
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Application opens on company website
Job Description
This role involves leading the Signal and Power Integrity strategy for high-performance storage platforms, overseeing electrical architecture, and collaborating with cross-functional teams to ensure system reliability, performance, and compliance in a cutting-edge technology environment.
Key Responsibilities
- Lead the Signal and Power Integrity (SI/PI) strategy for high-performance storage platforms.
- Own the electrical architecture from concept to lab validation and compliance sign-off.
- Architect and manage SI strategies for high-speed interfaces such as PCIe Gen5, 800G Ethernet, DDR5.
- Establish and validate Power Delivery Network (PDN) targets, including impedance profiling and decoupling optimization.
- Define and enforce global design standards in collaboration with PCB and mechanical teams.
- Lead system-level debug, root-cause analysis, and corrective actions for critical issues.
- Develop and standardize automated simulation workflows, reporting pipelines, and CI checks.
Requirements
- Expert-level proficiency in high-speed channel design and validation for modern interfaces such as PCIe Gen4, PCIe Gen5, 25G SerDes Ethernet, DDR4, and DDR5, including deep knowledge of electromagnetic (EM) theory, crosstalk mitigation, and jitter analysis.
- Mastery of industry-standard Electronic Design Automation (EDA) tools such as Sigrity, Advanced Design System (ADS), HFSS, and HyperLynx for pre- and post-layout Signal Integrity (SI) and Power Integrity (PI) analysis, including IBIS-AMI, channel modeling, and hands-on lab validation using high-speed instruments like VNA, TDR, BERT, and oscilloscopes.
- Advanced Power Integrity design experience in target impedance methodology, Voltage Regulator Module (VRM) modeling, noise coupling analysis, and defining component placement strategies to mitigate simultaneous switching noise (SSN) and ground bounce.
- Demonstrated ability to lead technical initiatives and drive complex cross-functional decisions, acting as a facilitator and mentor to junior engineers, and documenting best practices to champion quality by design.
- Fluency in developing scripts using Python and MATLAB for automating SI and PI model extraction, simulation workflows, post-processing, and generating standardized reports.
- Experience in defining and enforcing global design standards by collaborating with PCB layout and mechanical teams on stackups, materials, routing rules, and constraints to achieve first-pass silicon success and manufacturing quality.
- Ability to serve as the SI and PI technical lead for complex system-level debugging, root-cause analysis, and implementing corrective actions to resolve critical issues across prototypes, validation, and field escalations.
- Proficiency in designing and validating high-speed interfaces such as PCIe Gen5, 800G Ethernet, DDR5, ensuring product reliability and maximizing performance margins from initial link budgets through production release.
- Experience in establishing and validating Power Delivery Network (PDN) targets, including impedance profiling and decoupling optimization.
- Ability to work in an in-office environment at the Santa Clara, CA location in compliance with company policies, unless on PTO, work travel, or other approved leave.
Benefits & Perks
Salary range: 175,000 - 263,000 USD
Work environment: primarily in-office at Santa Clara, CA
Perks: flexible time off, wellness resources, company-sponsored team events
Potential eligibility for incentive pay and/or equity
Ready to Apply?
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