Job Description
The ROIC Layout Lead is responsible for the physical design, integration, and layout of large-scale ASICs, ROICs, and IP blocks, working closely with chip leads and foundries to ensure successful tapeout and optimal circuit performance.
Key Responsibilities
- Design and integrate large-scale ASIC, ROIC, and IP blocks through shuttle runs and prototype designs
- Coordinate with foundries to develop and execute tapeout activities
- Architect physical floor plans and layout circuit blocks in collaboration with chip leads
- Coordinate additional layout resources as needed to ensure efficient integration
- Perform custom layout of devices and circuit blocks considering constraints like pitch, yield, radiation hardness, and low noise
Requirements
- At least 10 years of experience as an IC Layout engineer working with mixed signal ASICs or large-scale IC blocks.
- Good communication skills, working effectively with circuit designers to iterate optimal design requirements.
- Strong proficiency in CAD tools including Cadence Virtuoso, Calibre DRC LVS LPE, and Assura.
- Knowledge of digital top and analog top design workflows.
- Understanding of deep sub-micron layout design practices such as metal density rules, transistor and capacitor matching, as well as mixed signal and yield improvement strategies.
- Ability to troubleshoot and resolve LVS and DRC errors, including the ability to spot schematic errors such as mislabeled or connected power and ground nets.
- Strong background in performing full custom analog IC layout.
- Proficiency in using computers, engineering workstations, complex electronic equipment, and interacting with vendors and colleagues.
- Willingness to work in a fast-paced, deadline-driven environment.
- Ability to work well in a team and independently.
- U.S. citizenship is required.
- Must be able to obtain and maintain a security clearance.
Benefits & Perks
Salary range of 145,745 - 186,688 USD
Bonus benefits
Ready to Apply?
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