Lead Cybersecurity Research Engineer – Embedded Systems

GE Vernova

Niskayuna, United States

Full Time

Posted September 3, 2026

$98k - $98k

Power Generation

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Listing evidence and provenance

Source: workday View original listing
Freshness: Open in the current public read path; this is not an employer guarantee.Last observed October 1, 2026
Classification: Modern power-system classification not yet published for this listing.Legacy source industry field: Power Generation
Pay provenance: Employer-provided pay

Job Description

As a Lead Cybersecurity Research Engineer at GE Vernova's Advanced Research Center, you will support R&D eﬀorts to secure critical embedded systems and industrial control environments.

Key Responsibilities

Support Cybersecurity technology development as a core contributor on R&D programs.
Assist in identifying and pursuing external funding opportunities for advanced research in the OT cybersecurity space.
Contribute to proposal activities by providing technical input and domain expertise.
Collaborate with universities, national laboratories, industrial consortiums, and commercial partners to advance the state of the art in OT cybersecurity for embedded systems.
Support technology roadmap execution with GE Vernova businesses and assist in the development of OT cybersecurity technologies for embedded systems from early-stage laboratory demonstrations to ﬁeldable prototypes.
Assist in deﬁning technical requirements and system-level security considerations across complex embedded and industrial control environments.
Support the maturation and transition of research technologies into GE Vernova product platforms in partnership with business and product teams.
Contribute to technical papers, patent ﬁlings, and open-source community engagement.
Participate in technical reviews, program reviews, and sponsor meetings.

Requirements

Ph.D. degree in Computer Science, Electrical Engineering, or a related field, with at least 1-3 years of industry experience.
Bachelor or master’s degree in computer science, Electrical Engineering, or a related ﬁeld, with at least 3-5 years of industry experience.
A minimum of 3-5 years of professional experience in embedded systems, ﬁrmware, or edge software development.
Current embedded programming capability in languages such as C, C++, and Python.
3+ years of experience working on cryptographic standards (TLS, X.509) and hardware-based security (HSM, TPM, ARM Trust Zone, secure boot).
3+ years of experience with or exposure to hardware-based security techniques such as HSM, TPM, ARM Trust Zone, secure boot, and related technologies.
3+ years of of embedded software development, computer architecture, Linux OS, and network protocols.
3+ years of experience with Linux security and driver development.
Familiarity with OT network design such as Purdue Model, segmentation, VLANs, ﬁrewalls, and zero-trust architectures in OT environments.
Exposure to threat modeling methodologies such as STRIDE or ATT&CK for ICS to identify vulnerabilities in physical processes, not just software stacks.
Familiarity with OT security standards speciﬁc to Operational Technology and practices such as IEC 62443, NERC CIP, NIST 800-82, SBOM, and secure ﬁrmware updates.
Exposure to ICS/SCADA architectures such as PLCs, RTUs, HMIs, historians, ﬁeldbus, edge gateways, and DMZ patterns.
Familiarity with industrial protocols such as Modbus/TCP, Modbus RTU, DNP3, EtherNet/IP, PROFINET, OPC UA/DA, BACnet, IEC 60870-5-104, IEC 61850, MQTT, and CAN/CANopen.
Exposure to real-time operating systems such as VxWorks, QNX, FreeRTOS, or similar platforms.
Exposure to real-time embedded systems, microcontrollers, FPGAs, x86, and/or ARM processors.
Must be willing to work out of an office located in Niskayuna, NY
Legal authorization to work in the US is required. We will not sponsor individuals at the Bachelor's level for employment visas, now or in the future, for this job opening.
GE Vernova will only employ those who are legally authorized to work in the United States for this opening. Any offer of employment is conditioned upon the successful completion of a drug screen (as applicable).