Job Description
The IC Layout Engineer is responsible for executing floor-planning and layout of semiconductor chip designs, supporting full chip integration, and resolving design errors using specialized tools, with a focus on deep sub-micron technologies.
Key Responsibilities
- Execute floor-planning and layout of block and chip-level designs for semiconductor IC technologies
- Support full chip integration mask-reticle assembly
- Resolve LVS and DRC errors in layout designs
- Apply deep sub-micron layout design practices such as metal density rules and transistor/capacitor matching
- Communicate layout requirements effectively with circuit designers
- Customize and generate standard cells for automated digital design flows (bonus)
Requirements
- Execute floor-planning and layout of block and chip-level designs in a variety of semiconductor Integrated chip technologies.
- Support full chip integration mask-reticle assembly.
- Have 2 years of experience in physical layout design across a variety of silicon and III-V semiconductor IC technologies.
- Experience with Cadence Virtuoso, Calibre DRC LVS LPE, and Assura.
- Must be able to resolve LVS DRC errors.
- Knowledge of deep sub-micron layout design practices such as metal density rules, transistor matching, and capacitor matching.
- Ability to communicate effectively with circuit designers to flow down layout requirements.
- Hold a BS or MS degree in Electrical Engineering, Computer Science, or a Related Discipline.
- U.S. citizenship is required.
- Must be able to obtain and maintain a security clearance.
Benefits & Perks
Base salary range of $99,705 - $124,683
Bonus benefits
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